Our Technology

The main areas of our work have concentrated on improving and expanding the performance envelope of technical materials by altering their morphology and manipulating fundamental energies.

Our Thinning Techniques allow membrane dimensions to influence all physical parameters.
Our ‘Back-End’ Technology enhances IC device ‘speed and output’ beyond the capabilities of ‘dimension scaling’. Our patented technology applies tensile stress mechanically to thinned, fabricated chips. Our process doubles CMOS output and speed. This is independent of device feature size. It is a macro-process, which has atomic-scale influence and is applicable to every micro-electronic device all the way down to quantum devices. We apply strain after IC fabrication is complete, taking full advantage of all state-of-the-art processing. Ours is an enabling technology, yielding single event Radiation hard properties along with enhanced performance.

Tensile strain increases mobility and decreases the band gap; making strained-silicon essentially a new material. Our Technology has general application ranging from mainstream electronics CMOS

CONGRESSIONAL Plus 2005-2008 “Next Again Generation Radiation Hard CMOS”
NSF 2003-2007 “Ge-Free Strained Silicon Via dTCE Bonding”
BAA DARPA/MTO 2003-2004 “Novel Approach to Ultra-High-Speed, Fully
Integrated Bipolar and Unipolar Devices”
SBIR MDA 2003-2004 “Gallium Nitride Device Technology”
SBIR MDA 2002-2003 “Strain-Enhanced Tunnel Diode Technology”
BAA ONR 2000-2001 As part of “Long Range Scientific and Technology Research
in Semiconductor Materials”

Present & Future

We are currently determining the electronic effects of high level straining on a number of CMOS architectures. In the pipeline are four novel uniaxial and three biaxial straining procedures. We are currently looking to expand our company to include a research base in opto-electronics technology.